Robustness of TAP-based Scan Networks

It is common to embed instruments when developing integrated circuits (ICs). These instruments are accessed at post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and operator-driven in-field test. At any of these scenarios, it is of interest to access some but not all of the instruments. IEEE 1149.1-2013 and IEEE 1687 propose Test Access Port based (TAP-based) mechanisms to design flexible scan networks such that any combination of instruments can be accessed from outside of the IC. Previous works optimize TAP-based scan networks for one scenario with a known number of accesses. However, at design time, it is difficult to foresee all needed scenarios and the exact number of accesses to instruments. Moreover, the number of accesses might change due to late design changes, addition/exclusion of tests, and changes of constraints. In this paper, we analyze and compare seven IEEE 1687 compatible network design approaches in terms of instrument access time, hardware overhead, and robustness. Given the similarities between IEEE 1149.1-2013 and IEEE 1687, the conclusions are also applicable to IEEE 1149.1-2013 networks

A Self-Reconfiguring IEEE 1687 Network for Fault Monitoring

Efficient handling of faults during operation is highly dependent on the interval (latency) from the time embedded instruments detect errors to the time when the fault manager localizes the errors. In this paper, we propose a self-reconfiguring IEEE 1687 network in which all instruments that have detected errors are automatically included in the scan path. To enable self-reconfiguration, we propose a modified segment insertion bit (SIB) compliant to IEEE 1687. We provide time analyses on error detection and fault localization for single and multiple faults, and we suggest how the self-reconfiguring IEEE 1687 network should be designed such that time for error detection and fault localization is kept low and deterministic. For validation, we implemented and performed post-layout simulations for one self-reconfiguring network. We show that compared to previous schemes, our proposed network significantly reduces the fault localization time

Access Time Minimization in IEEE 1687 Networks

IEEE 1687 enables flexible access to the embedded (on-chip) instruments that are needed for post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and in-field test. At any of these scenarios, the instruments are accessed differently, and at a given scenario the instruments are accessed differently over time. It means the IEEE 1687 network needs to be frequently reconfigured from accessing one set of instruments to accessing a different set of instruments. Due to the need of frequent reconfiguration of the IEEE 1687 network it is important to (1) minimize the run-time for the algorithm finding the new reconfiguration, and (2) generate scan vectors with minimized access time. In this paper we model the reconfiguration problem using Boolean Satisfiability Problem (SAT). Compared to previous works we show significant reduction in run-time and we ensure minimal access time for the generated scan vectors

Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus

Accessing embedded test and monitoring circuitry (the so-called embedded instruments) in in-field products can reduce maintenance and diagnostics costs. Performing such access can be facilitated when done over an internal system bus, due to that it might be faster and less cumbersome to reach a system processor (on an in-field product) over a network interface, compared with the effort and speed of gaining access to a test interface on the same product. Enabling such access might require that, at the component level, the embedded instruments in a system-on-chip (SoC) become accessible both from a chip interface and from an on-chip processor over a system bus. Although this reuse of embedded instruments can be achieved by already existing standards, such as IEEE 1687, the system bus might become a scalability bottleneck when the number of instruments that are to be reused increases. In this paper, we propose two solutions that address the scalability in this type of reuse while maintaining compatibility with IEEE 1687 tools. We also discuss the trade-offs associated with each approach and present timing analyses that by considering system parameters such as clock rates determine how the correct operation can be guaranteed. To validate the proposed solutions, we have implemented them on an FPGA using AXI as system bus, and have used standard IEEE 1687 tools to access the instruments. We present some details of the implementation to highlight practical issues such as clock domain crossing, as well as how the presented timing analyses can be used to adjust design parameters

Reconfigurable On-Chip Instrument Access Networks : Analysis, Design, Operation, and Application

The constant need for higher performance and more advanced functionality has made the design and manufacturing of modern electronic chips highly demanding. Moreover, the use of smaller transistors in modern chips has increased their sensitivity to aging and faults, hence the need to constantly monitor the correct operation of these chips. To address the challenges and requirements, it has become common to embed extra hardware modules in the chips to assist in the design and manufacturing processes, as well as in monitoring the correct operation of the chips. Such modules, commonly referred to as on-chip instruments, are used through the entire life cycle of the chip, from the early prototyping phase to when the system incorporating that chip becomes operational at the customer's site. The increasing trend in the number and complexity of the on-chip instruments called for methodologies that allow for scalable, fast, and easy access to these instruments. As an alternative to in-house methods, which although effective might be expensive to maintain, two IEEE standards, namely, IEEE Std 1687 and IEEE Std 1149.1-2013, have recently come into existence. These standards provide a common base for describing reconfigurable on-chip instrument access networks, as well as for describing the operation of each embedded instrument by using high-level description languages. Such common base motivates the development of relevant design automation tools, and facilitates the integration of instruments developed by multiple vendors. These standards, however, have left the arising optimization problems in the design and operation of such networks to be addressed by the electronic design automation community. In this thesis, we address some of these optimization problems whose objective is to minimize the instrument access time, i.e., the time it takes to transport data to/from the instruments over reconfigurable on-chip instrument access networks. In particular, we present access time analysis that helps to determine the contributing factors to the access time overhead. Using the analysis, we present methods for design of reconfigurable networks that are optimized with respect to instrument access time. Moreover, to operate such on-chip networks, there is a need for automation tools that translate (retarget) high-level descriptions of instrument access procedures specified at instruments' boundaries, into low-level description languages or bit vectors applicable from the chip's boundary. The reconfigurability of these networks, makes it challenging to perform the retargeting such that the generated vectors are optimized with respect to the time it takes to apply them to the chip. In this thesis, we explore opportunities for optimization in retargeting. In particular, we present a method to assist in optimal bit vector generation, by reducing the solution space without removing the optimal vector from it. Finally, considering the application of on-chip networks in in-field monitoring of the correct operation of chips, we propose a self-reconfiguring network that upon detection of errors, automatically reconfigures itself to reduce the time it takes to identify the faulty resources

Analysis and Optimization for Testing Using IEEE P1687

 The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded test, debug and monitoring logic (instruments), such as scan-chains and temperature sensors, and the Test Access Port of IEEE Standard 1149.1 mainly used for board test. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan path. SIBs make it possible to construct a multitude of different P1687 networks for the same set of instruments, and provide flexibility in test scheduling. The work presented in this thesis consists of two parts. In the first part, analysis regarding test application time is given for P1687 networks while making use of two test schedule types, namely concurrent and sequential test scheduling. Furthermore, formulas and novel algorithms are presented to compute the test time for a given P1687 network and a given schedule type. The algorithms are implemented and employed in extensive experiments on realistic industrial designs. In the second part, design of IEEE P1687 networks is studied. Designing the P1687 network that results in the least test application time for a given set of instruments, is a time-consuming task in the absence of automatic design tools. In this thesis work, novel algorithms are presented for automated design of P1687 networks which are optimized with respect to test application time and the required number of SIBs. The algorithms are implemented and demonstrated in experiments on industrial SOCs.

Accessing On-chip Instruments Through the Life-time of Systems

The electronic systems we find in almost every product today are implemented using integrated circuits (ICs) mounted on printed circuit boards (PCBs). Developing electronic systems is a challenging task due to complexity and miniaturization. A single IC can contain billions of transistors, which are smaller than ever. As a result more Design-for-Test (DfT) features, so called instruments, are embedded on-chip in modern ICs to handle and monitor various activities. Many defects are handled at IC manufacturing; however, there are many problems occurring after ICs are being mounted on PCBs. In many cases, it is unfortunately not possible to reproduce the problem when the electronic system is taken to a repair shop. These problems are known as No Trouble Found (NTF). One obstacle is the limited access to the on-chip DfT instruments that exist in most ICs. We will discuss access to on-chip DfT instruments through the life-time of electronic systems. We will focus on electronic systems using the IEEE 1687 standard

Accessing Embedded DfT Instruments with IEEE P1687

While the advancement in semiconductor technologies enables manufacturing of highly advanced and complex integrated circuits, there is an increasing need of embedded (on-chip) instruments for test, debug, diagnosis, configuration, monitoring, etc. A key challenge is how to access these instruments from chip terminals in a low-cost, non-intrusive, standardized, flexible and scalable manner. The well-adopted IEEE 1149.1 (Joint Test Action Group (JTAG)) standard offers low-cost, non- intrusive and standardized access but lacks flexibility and scalability, which is addressed by the on-going IEEE P1687 (Internal JTAG (IJTAG)) standardization initiative. This paper discusses the need of embedded instrumentation, the shortcomings of IEEE 1149.1 as well as features and challenges of IEEE P1687